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r technical data xc5200 logic cell array family preliminary (v1.0) april 1995
r and xact are registered trademarks of xilinx. all xc- pre?x product designations, xact-performance, x-blox, xchecker, xdm, lca, logic cell, express, versablock, and versaring are trademarks of xilinx. the programmable logic company and the programmable gate array company are service marks of xilinx. mentor is a registered trademark and neted, design architect, quicksim, and quicksim ii are trademarks of mentor graphics, inc. orcad is a registered trademark of orcad systems corporation. viewlogic, viewsim, and viewdraw are registered trademarks of viewlogic systems, inc. synopsys is a registered trademark of synopsys, inc. xilinx does not assume any liability arising out of the application or use of any product described herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. xilinx devices and products are protected under one or more of the following u.s. patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,783,607; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,267,187; 5,224,056; 5,245,277; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; re 34,363; re 34,444; and re 34,808. xilinx, inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third-party right. xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. xilinx products are not intended for use in life support appliances, devices, or systems. use of a xilinx product in such applications without the written consent of the appropriate xilinx of?cer is prohibited.
r table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 xc5200 family compared to xc4000 family . . . . . . . . . . . . . . . . . . . . . . . . . 2 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 detailed functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 versablock routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 general routing matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

r 1 xc5200 logic cell array family preliminary (v1.0) product description table 1. initial xc5200 field-programmable gate array family members device xc5202 xc5204 xc5206 xc5210 xc5215 typical gate range 2,200 - 2,700 3,900 - 4,800 6,000 - 7,500 10,000 - 12,000 14,000 - 18,000 versablock array 8 x 8 10 x 12 14 x 14 18 x 18 22 x 22 number of clbs 64 120 196 324 484 number of flip-flops 256 480 784 1,296 1,936 number of i/os 84 124 148 196 244 tbufs per horizontal longline 10 14 16 20 24 ? fully supported by xact ? development system includes complete support for xact-performance?, x-blox?, uni?ed libraries, relationally placed macros (rpms), xdelay, and xchecker? wide selection of pc and workstation platforms interfaces to more than 100 third-party cae tools description the xc5200 field-programmable gate array family is engineered to deliver the lowest cost of any fpga family. by optimizing the new xc5200 architecture for tlm technology and 0.6- m m cmos sram process, dramatic advances have been made in silicon ef?ciency. these advances position the xc5200 family as a cost-effective, high-volume alternative to gate arrays. building on experiences gained with three previous successful sram fpga families, the xc5200 family brings a robust feature set to high-density programmable logic design. the versablock logic module, the versaring i/o interface, and a rich hierarchy of interconnect resources combine to enhance design ?exibility and reduce time-to-market. complete support for the xc5200 family is delivered through the familiar xact software environment. the xc5200 family is fully supported on popular workstation and pc platforms. popular design entry methods are fully supported, including abel, schematic capture, and synthesis. designers utilizing logic synthesis can use their existing synopsys, viewlogic, mentor, and exemplar tools to design with the xc5200 devices. features ? high-density family of field-programmable gate arrays (fpgas) ? design- and process-optimized for low cost 0.6- m m three-layer metal (tlm) process ? system performance up to 50 mhz ? sram-based, in-system reprogrammable architecture ? flexible architecture with abundant routing resources versablock? logic module versaring? i/o interface dedicated cell-feedthrough path hierarchical interconnect structure extensive registers/latches dedicated carry logic for arithmetic functions cascade chain for wide input functions dedicated ieee 1149.1 boundary-scan logic internal 3-state bussing capability four global low-skew clock or signal distribution nets globally selectable cmos or ttl input thresholds output slew-rate control 8-ma sink current per output ? con?gured by loading binary ?le unlimited reprogrammability six programming modes, including high-speed express? mode ? 100% factory tested ? 100% footprint compatibility for common packages
xc5200 logic cell array family preliminary (v1.0) 2 xc5200 family compared to xc4000 family for those readers already familiar with the xc4000 family of xilinx field-programmable gate arrays, here is a concise description of the similarities and differences between the xc4000 and xc5200 families. super?cially, the xc5200 family is quite similar to the xc4000 family. both use cmos sram technology. both use 4-input lookup tables with unshared inputs. both have a dedicated fast carry track, and dedicated boundary-scan logic in the input/output blocks (iobs). xc5200 and xc4000 devices are footprint and pin-out compatible; their pin names and pin locations are identical. xc5200 devices offer the same con?guration options as xc4000 devices, and they can be intermixed with xc4000 devices in a con?guration daisy chain. there are also, however, signi?cant differences between the two families: ? xc5200 lookup tables cannot be used as ram. ? the xc5200 family offers dedicated carry logic, but differs from the xc4000 family in that the sum is generated in an additional function generator in the adjacent column. an xc5200 device thus uses twice as many function generators for adders, subtracters, accumulators, and some counters. note, however, that a loadable up/down counter requires the same number of function generators in both families. ? xc5200 devices have no dedicated wide edge decoders. the xc5200 carry logic, unlike the xc4000 architecture, can be used to cascade function generators to implement wide and and or functions, for example. ? the xc5200 family contains a ?exible coupling of logic and local routing resources called the versablock. the xc5200 versablock element includes the con?gurable logic block (clb), a local interconnect matrix (lim), and direct connects to neighboring versablocks. ? xc5200 clbs are roughly equivalent to two xc4000 clbs. each xc5200 clb contains four 4-input function generators and four registers, which are con?gured as four independent logic cells? (lcs). the output from each function generator can be brought out as a clb output and/or drive the d input of a ?ip-?op. pairs of logic cells can be combined to form a 5-input function generator. ? there are four direct feedthrough paths per clb, one per lc. these paths can provide extra data input lines or serve as local routes without consuming any logic resources. ? the xc5200 family has a global reset, whereas the xc4000 family has both a global set and a global reset. ? unlike the xc4000 family, each register can be con?gured as either an edge-triggered d ?ip-?op or a transparent, level-sensitive latch. ? there are no dedicated iob ?ip-?ops, but there are fast direct connects to adjacent clbs. table 2. four generations of xilinx field-programmable gate array families parameter xc5200 xc4000 xc3000a/XC3100A xc2000 function generators per clb 4322 logic inputs per clb 20954 logic outputs per clb 12422 low-skew global buffers 4822 user ram no yes no no dedicated decoders no yes no no cascade chain yes no no no fast carry logic yes yes no no internal 3-state drivers yes yes yes no ieee boundary scan yes yes no no output slew-rate control yes yes yes no power-down option no no yes yes crystal oscillator circuit no no yes yes
r 3 ? the tlm process allows signi?cant improvements in the routing structure. each xc5200 versablock element has complete intra-clb routing, the lim, and offers four direct routing connections to each of the four neighboring clbs (north, south, east, and west). any function generator or ?ip-?op thus has unrestricted connectivity to 19 other function generators or ?ip- ?ops: three in its own clb, and 16 in the adjacent clbs. these direct connects do not compete with the general routing resources (see table 3). ? each xc5200 3-state buffer (tbuf) can drive up to two horizontal longlines; each xc4000 tbuf accesses only one horizontal longline. ? there is a special racetrack, the versaring, between the outer edge of the core clb array and the ring of iobs, providing signi?cant help in overcoming the problems caused by early locking of i/o pins. ? there are no internal pull-ups for xc5200 longlines. figure 1. xc5200 architectural overview table 3. routing resource comparison resource xc5200 xc4000 single-length lines 10 8 double-length lines 44 longlines 86 direct connects 80 versaring yes no x4955 grm input/output blocks (iobs) versa- block grm versa- block versaring versaring grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block versaring versaring architectural overview figure 1 presents a simpli?ed, conceptual overview of the xc5200 architecture. similar to conventional fpgas, the xc5200 family consists of programmable iobs, programmable logic blocks, and programmable interconnect. unlike other fpgas, however, the logic and local routing resources of the xc5200 family are combined in ?exible versablocks. general-purpose routing connects to the versablock through the general routing matrix (grm). versablock: abundant local routing plus versatile logic the basic logic element in each versablock structure is the logic cell, shown in figure 2. each lc contains a 4- input function generator (f), a storage device (fd), and control logic. there are ?ve independent inputs and three outputs to each lc. the independence of the inputs and outputs allows the software to maximize the resource utilization within each lc. each logic cell also contains a direct feedthrough path that does not sacri?ce the use of either the function generator or the register; this feature is a ?rst for fpgas. the storage device is con?gurable as either a d ?ip-?op or a latch. the control logic consists of carry logic for fast implementation of arithmetic functions, which can also be con?gured as a cascade chain allowing decode of very wide input functions. the xc5200 clb consists of four lcs, as shown in figure 3. each clb has 20 independent inputs and 12 independent outputs. the top and bottom pairs of lcs can be con?gured to implement 5-input functions. the challenge of fpga implementation software has always been to maximize the usage of logic resources. the xc5200 family addresses this issue by surrounding each clb with two types of local interconnect the lim and direct connects. these two interconnect resources, combined with the clb, form the versablock, represented in figure 4. figure 2. xc5200 logic cell (four lcs per clb) x4956 f4 f3 f fd f2 f1 dq x do di co ci ce ck clr
xc5200 logic cell array family preliminary (v1.0) 4 figure 3. con?gurable logic block x4957 f4 f3 f fd lc3 lc2 lc1 lc0 f2 f1 dq x do di co f4 f3 f fd f2 f1 dq x do di f4 f3 f fd f2 f1 dq x do di f4 f3 f fd f2 f1 dq x do di ci ce ck clr lc0 figure 4. versablock the lim provides 100% connectivity of the inputs and outputs of each lc in a given clb. the bene?t of the lim is that no general routing resources are required to connect feedback paths within a clb. the lim connects to the grm via 24 bidirectional nodes. the direct connects allow immediate connections to neighboring clbs, once again without using any of the general interconnect. these two layers of local routing resource improve the granularity of the architecture, effectively making the xc5200 family a sea of logic cells. each versablock has four 3-state buffers that share a common enable line and directly drive horizontal longlines, creating robust on-chip bussing capability. the versablock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. these resources also minimize local routing congestion and improve the ef?ciency of the general interconnect, which is used for connecting larger groups of logic. it is this combination of both ?ne-grain and coarse-grain architecture attributes that maximize logic utilization in the xc5200 family. this symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions. x5707 clb direct connects ts grm lim 4 4 4 4 4 lc3 lc2 lc1 lc0 4 4 44 24 24
r 5 versaring i/o interface the interface between the iobs and core logic has been redesigned in the xc5200 family. the iobs are completely decoupled from the core logic. the xc5200 iobs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. this approach allows a maximum number of iobs to be placed around the device, improving the i/o-to- gate ratio and decreasing the cost per i/o. a freeway of interconnect cells surrounding the device forms the versaring, which provides connections from the iobs to the internal logic these incremental routing resources provide abundant connections from each iob to the nearest versablock, in addition to longline connections surrounding the device. the versaring eliminates the historic trade-off between high logic utilization and pin placement ?exibility. these incremental edge resources give users increased ?exibility in preassigning (i.e., locking) i/o pins before completing their logic designs. this ability accelerates time-to-market, since pcbs and other system components can be manufactured concurrent with the logic design. general routing matrix the grm is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the versablocks. advanced simulation tools were used during the development of the xc5200 architecture to determine the optimal level of routing resources required. the xc5200 family contains six levels of interconnect hierarchy a series of single-length lines, double-length lines, and longlines all routed through the grm. the direct connects, lim, and logic-cell feedthrough are contained within each versablock. throughout the xc5200 interconnect, an ef?cient multiplexing scheme, in combination with tlm, was used to improve the overall ef?ciency of silicon usage. performance overview the xc5200 family has been benchmarked with many designs running synchronous clock rates up to 40 mhz. the performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. table 4 shows some performance numbers for representative circuits, using worst-case timing parameters for the engineering sample (es) speed grade. a rough estimate of timing can be made by assuming 6 ns per logic level, which includes direct-connect routing delays. more accurate estimations can be made using the information in the switching characteristic guideline section. table 4. performance for several common circuit functions function xc5200 speed grade -6 -5 -4 16-bit decoder from input pad 9ns 8ns 24-bit accumulator 32 mhz 39 mhz 16-to-1 multiplexer 16 ns 13 ns 16-bit unidirectional loadable counter 40 mhz 50 mhz 16-bit u/d counter 40 mhz 50 mhz 16-bit adder 24 ns 20 ns 24-bit loadable u/d counter 36 mhz 42 mhz
xc5200 logic cell array family preliminary (v1.0) 6 development system the powerful features of the xc5200 device family require an equally powerful, yet easy-to-use, set of development tools. xilinx provides an enhanced version of the xilinx automatic cae tools (xact), optimized for the xc5200 family. as with other logic technologies, the basic methodology for xc5200 fpga design consists of three interrelated steps: design entry, implementation, and veri?cation. popular generic tools are used for entry and simulation (for example, viewlogic systemss viewdraw schematic editor and viewsim simulator), but architecture-speci?c tools are needed for implementation. all xilinx development system software is integrated under the xilinx design manager (xdm?), providing designers with a common user interface regardless of their choices of entry and veri?cation tools. xdm simpli?es the selection of command-line options with pull-down menus and online help text. application programs ranging from schematic capture to partitioning, placement, and routing (ppr) can be accessed from xdm, while the program-command sequence is generated and stored for documentation prior to execution. the xmake command, a design compilation utility, automates the entire implementation process, automatically retrieving the designs input ?les and performing all the steps needed to create con?guration and report ?les. several advanced features of the xact system facilitate xc5200 fpga design. rpms schematic-based macros with relative location constraints to guide their placement within the fpga help to ensure an optimized implementation for common logic functions. an abundance of local routing permits rpms to be contained within a single versablock or to span across multiple versablocks. xact-performance allows designers to enter the exact performance requirements during design entry, at the schematic level, to guide ppr. design entry designs can be entered graphically, using schematic- capture software, or in any of several text-based formats (such as boolean equations, state-machine descriptions, and high-level design languages). xilinx and third-party cae vendors have developed library and interface products compatible with a wide variety of design-entry and simulation environments. a standard interface-?le speci?cation, xilinx netlist file (xnf), is provided to simplify ?le transfers into and out of the xact development system. xilinx offers xact development system interfaces to the following design environments: ? viewlogic systems (viewdraw, viewsim) ? mentor graphics v8 (neted, quicksim, design architect, quicksim ii) ? orcad (sdt, vst) ? synopsys (design compiler, fpga compiler) ? xilinx-abel (state machine module generator) ? x-blox (graphical mode generator) many other environments are supported by third-party vendors. currently, more than 100 packages are supported. the uni?ed schematic library for the xc5200 fpga re?ects the wide variety of logic functions that can be implemented in these versatile devices. the library contains over 400 primitives and macros, ranging from 2- input and gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, i/o functions, latches, boolean functions, multiplexers, shift registers, and barrel shifters. designing with macros is as easy as designing with standard ssi/msi functions. the soft macro library contains detailed descriptions of common logic functions, but does not contain any partitioning or routing information. the performance of these macros depends, therefore, on how the ppr software processes the design. rpms, on the other hand, do contain predetermined partitioning and relative placement information, resulting in an optimized implementation for these functions. users can create their own library elements either soft macros or rpms based on the macros and primitives of the standard library. the x-blox design language is a graphics-based high- level description language (hdl) that allows designers to use a schematic editor to enter designs as a set of generic modules. the x-blox compiler synthesizes and optimizes the modules for the target device architecture, automatically choosing the appropriate architectural resources for each function. the xact design environment supports hierarchical design entry, with top-level drawings de?ning the major functional blocks, and lower-level descriptions de?ning the logic in each block. the implementation tools automatically combine the hierarchical elements of a design. different hierarchical elements can be speci?ed with different design entry tools, allowing the use of the most convenient entry method for each portion of the design.
r 7 design implementation the design implementation tools satisfy the requirements for an automated design process. logic partitioning, block placement, and signal routing are performed by the ppr program. the partitioner takes the logic from the entered design and maps the logic into the architectural resources of the fpga (such as the logic blocks, i/o blocks, and 3- state buffers). the placer then determines the best locations for the blocks, depending on their connectivity and the required performance. the router ?nally connects the placed blocks together. the ppr algorithms support fully automatic implementation of most designs. however, for demanding applications, the user may exercise various degrees of control over the automated implementation process. optionally, user-designated partitioning, placement, and routing information can be speci?ed as part of the design- entry process. the implementation of highly structured designs can bene?t greatly from the basic ?oorplanning techniques familiar to designers of large gate arrays. the ppr program includes xact-performance, a feature that allows designers to specify the timing requirements along entire paths during design entry. timing path analysis routines in ppr then recognize and accommodate the user-speci?ed requirements. timing requirements can be entered on the schematic in a form directly relating to the system requirements (such as the targeted minimum clock frequency, or the maximum allowable delay on the data path between two registers). so, while the timing of each individual net is not predictable, the overall performance of the system along entire signal paths is automatically tailored to match user- generated speci?cations. design veri?cation the high development cost associated with common mask-programmed gate arrays necessitates extensive simulation to verify a design. due to the custom nature of masked gate arrays, mistakes or last-minute design changes cannot be tolerated. a gate-array designer must simulate and test all logic using simulation software. simulation describes what happens in a system under worst-case situations. however, simulation can be tedious and slow, and simulation vectors must be generated. a few seconds of system time can take weeks to simulate. programmable-gate-array users, however, can use in- circuit debugging techniques in addition to simulation. because xilinx devices are reprogrammable, designs can be veri?ed in real time without the need for extensive simulation vectors. the xact development system supports both simulation and in-circuit debugging techniques. for simulation, the system extracts the post-layout timing information from the design database. this data can then be sent to the simulator to verify timing-critical portions of the design database using xdelay, the xilinx static timing analyzer tool. back-annotation the process of mapping the timing information back into the signal names and symbols of the schematic eases the debugging effort. for in-circuit debugging, the xact development system includes a serial download and readback cable (xchecker) that connects the fpga in the system to the pc or workstation through an rs232 serial port. the engineer can download a design or a design revision into the system for testing. the designer can also single-step the logic, read the contents of the numerous ?ip-?ops on the device, and observe internal logic levels. simple modi?cations can be downloaded into the system in a matter of minutes.
xc5200 logic cell array family preliminary (v1.0) 8 figure 5. two luts in parallel combined to create a 5-input function out q qout do q d fd x fd co di x clr lc0 ck ce 5-input function d do f5_mux di f f4 f3 f2 f1 f4 f3 f2 f1 i1 i2 i3 i4 i5 ci f lc1 x5710 detailed functional description clb logic figure 3 shows the logic in the xc5200 clb, which consists of four logic cells (lc[3:0]). each logic cell consists of an independent 4-input lookup table (lut), and a d-type ?ip-?op or latch with common clock, clock enable, and clear, but individually selectable clock polarity. additional logic features provided in the clb are: ? high-speed carry propagate logic. ? high-speed pattern decoding. ? high-speed direct connection to ?ip-?op d-inputs. ? each ?ip-?op can be programmed individually as either a transparent, level-sensitive latch or a d ?ip-?op. ? four 3-state buffers with a shared output enable. ? two 4-input luts can be combined to form an independent 5-input lut. 5-input functions figure 5 illustrates how the outputs from the luts from lc0 and lc1 can be combined with a 2:1 multiplexer (f5_mux) to provide a 5-input function. the outputs from the luts of lc2 and lc3 can be similarly combined.
r 9 carry function the xc5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. a carry multiplexer (cy_mux) symbol on a schematic is used to indicate the xc5200 carry logic. this symbol represents the dedicated 2:1 multiplexer in each lc that performs the one-bit high- speed carry propagate per logic cell (four bits per clb). while the carry propagate is performed inside the lc, an adjacent lc must be used to complete the arithmetic function. figure 6 represents an example of an adder function. the carry propagate is performed on the clb shown, which also generates the half-sum for the four-bit adder. an adjacent clb is responsible for xoring the half-sum with the corresponding carry-out. thus an adder or counter requires two lcs per bit. notice that the carry chain requires an initialization stage, which the xc5200 family accomplishes using the carry initialize (cy_init) macro and one additional lc. the xc5200 library contains a set of rpms and arithmetic functions designed to take advantage of the dedicated carry logic. using and modifying these macros makes it much easier to implement customized rpms, freeing the designer from the need to become an expert on architectures. figure 6. xc5200 cy_mux used for adder carry propagate f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 xor xor xor xor f=0 di di di di fd fd fd fd carry out carry3 do d x lc3 do dq lc2 x ci carry in cy_mux cy_mux cy_mux cy_mux cy_mux x do do do do lc1 lc0 ck ce clr d d q q x q half sum0 carry0 half sum2 half sum1 carry1 carry2 half sum3 co a3 or b3 a3 and b3 to any two a2 and b2 to any two a2 or b2 a1 or b1 a1 and b1 to any two a0 or b0 a0 and b0 to any two 0 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 xor xor xor xor di di di di fd fd do fd fd d x lc3 do dq lc2 x ci x lc1 lc0 ck ce clr d d q q x q sum0 sum2 sum1 sum3 co initialization of carry chain (one logic cell) x5709
xc5200 logic cell array family preliminary (v1.0) 10 figure 7. xc5200 cy_mux used for decoder cascade logic f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 and and f=0 di di di di fd fd fd cascade out out do d x lc3 do do do dq lc2 x ci cascade in cy_mux cy_mux cy_mux cy_mux cy_mux fd x lc1 initialization of carry chain (one logic cell) lc0 ck ce clr d d q q x q co and and x5708 cascade function each cy_mux can be connected to the cy_mux in the adjacent lc to provide cascadable decode logic. figure 7 illustrates how the 4-input function generators can be con?gured to take advantage of these four cascaded cy_muxes. note that and and or cascading are speci?c cases of a general decode. in and cascading all bits are decoded equal to logic one, while in or cascading all bits are decoded equal to logic zero. the ?exibility of the lut achieves this result.
r 11 3-state buffers the xc5200 family has four dedicated tbufs per clb. the four buffers are individually con?gurable through four con?guration bits to operate as simple non-inverting buffers or in 3-state mode. when in 3-state mode the clbs output enable (ts) control signal drives the enable to all four buffers (see figure 8). each tbuf can drive up to two horizontal longlines oscillator the xc5200 oscillator (osc52) divides the internal 16- mhz clock or a user clock that is connected to the c pin. the user then has the choice of dividing by 4, 16, 64, or 256 for the osc1 output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the osc2 output. the division is speci?ed via a dividen_by=x attribute on the symbol, where n=1 for osc1, or n=2 for osc2. the osc5 macro is used where an internal oscillator is required. the ck_div macro is applicable when a user clock input is speci?ed (see figure 9). figure 8. xc5200 3-state buffer figure 9. xc5200 oscillator macros clb ts lc3 lc2 lc1 lc0 clb horizontal longlines x5706 osc5 osc1 osc2 ck_div osc1 osc2 clk start-up on start-up, all xc5200 internal ?ip-?ops are reset. the xc5200 devices do not support the init= attribute. thus, the xc5200 family has only a global reset (gr) signal. the user can assign the pin location for the gr signal and use it to reset asynchronously all of the ?ip- ?ops in the design without using general routing resources. the user can also assign a positive or negative polarity to gr. boundary scan xc5200 devices support all the mandatory boundary-scan instructions speci?ed in the ieee standard 1149.1. a test access port (tap) and registers are provided that implement the extest, sample/preload, and bypass instructions. the tap can also support two usercode instructions. boundary-scan operation is independent of individual iob con?guration and package type. all iobs are treated as independently controlled bidirectional pins, including any unbonded iobs. retaining the bidirectional test capability after con?guration provides ?exibility for interconnect testing. also, internal signals can be captured during extest by connecting them to unbonded iobs, or to the unused outputs in iobs used as unidirectional input pins. this technique partially compensates for the lack of intest support. the public boundary-scan instructions are always available prior to con?guration. after con?guration, the public instructions and any usercode instructions are only available if speci?ed in the design. while sample and bypass are available during con?guration, it is recommended that boundary-scan operations not be performed during this transitory period. in addition to the test instructions outlined above, the boundary-scan circuitry can be used to con?gure the logic cell array (lca?) device, and to read back the con?guration data. all of the xc4000 boundary-scan modes are supported in the xc5200 family. three additional outputs for the user register are provided (reset, update, and shift), representing the decoding of the corresponding state of the boundary-scan internal state machine. for details on boundary scan, refer to boundary scan in xc4000 devices application note on pages 8-45 through 8-42 of the 1994 xilinx programmable logic data book.
xc5200 logic cell array family preliminary (v1.0) 12 versablock routing local interconnect matrix the grm connects to the versablock via 24 bidirectional ports (m0-m23). excluding direct connections, global nets, and 3-statable longlines, all versablock inputs and outputs connect to the grm via these 24 ports. four 3- statable unidirectional signals (tq0-tq3) drive out of the versablock directly onto the horizontal longlines. two horizontal global nets (gh0 and gh1) and two vertical global nets (gv0 and gv1) connect directly to every clb clock pin; they can connect to other clb inputs via the grm. each clb also has four unidirectional direct connects to each of its four neighboring clbs. these direct connects can also feed directly back to the clb (see figure 10). in addition, each clb has 16 direct inputs, four direct connections from each of the neighboring clbs. these direct connections provide high-speed local routing that bypasses the grm. the 13 clb outputs (12 lc outputs plus a v cc /gnd signal) connect to the eight versablock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. of the eight versablock outputs, four signals drive each neighboring clb directly, and provide a direct feedback path to the input multiplexers. the four remaining multiplexer outputs can drive the grm through four tbufs (tq0-tq3). all eight multiplexer outputs can connect to the grm through the bidirectional m0-m23 signals. all eight signals also connect to the input multiplexers and are potential inputs to that clb. clb inputs have several possible sources: the 24 signals from the grm, 16 direct connections from neighboring versablocks, four signals from global, low-skew buffers (gh0, gh1, gv0, and gv1), and the four signals from the clb output multiplexers. unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given clb input. the ?exibility of lut input swapping and lut mapping compensates for this limitation. for example, if a 2-input nand gate is required, it can be mapped into any of the four luts, and use any two of the four inputs to the lut. direct connects the unidirectional direct-connect segments are connected to the logic input/output pins through the clbs input and output multiplexer array, and thus bypass the programmable routing matrix altogether. these lines are intended to increase the routing channel utilization where possible, while simultaneously reducing the delay incurred in speed-critical connections. the direct connects also provide a high-speed path from the edge clbs to the versaring input/output buffers, and thus reduce set-up time, clock-to-out, and combinational propagation delay. the direct connects are ideal for developing customized rpm cells. using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. direct connects can also route through a clb using one of the four cell-feedthrough paths.
r 13 figure 10. versablock details 4 4 4 4 5 5 5 5 3 3 3 3 24 to grm m0-m23 clb clk direct north direct to east to longlines and grm tq0-tq3 global nets feedback direct west direct south ce clr c in c out v cc /gnd ts 4 4 north 4 8 south 4 east 4 west 4 lc3 lc2 lc1 lc0 output multiplexers input multiplexers 8 4 4 4 x5724
xc5200 logic cell array family preliminary (v1.0) 14 general routing matrix the general routing matrix, shown in figure 11, provides ?exible bidirectional connections to the local interconnect matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. a programmable interconnect point (pip) establishes an electrical connection between two wire segments. the pip, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. a collection of pips inside the general routing matrix and in the local interconnect matrix provides connectivity between various types of metal segments. a hierarchy of pips and associated routing segments combine to provide a powerful interconnect hierarchy: ? forty bidirectional single-length segments per clb provide ten routing channels to each of the four neighboring clbs in four directions. ? sixteen bidirectional double-length segments per clb provide four routing channels to each of four other (non- neighboring) clbs in four directions. ? eight horizontal and eight vertical bidirectional longline segments span the width and height of the chip, respectively. ? two low-skew horizontal and vertical unidirectional global-line segments span each row and column of the chip, respectively. single- and double-length lines the single- and double-length bidirectional line segments make up the bulk of the routing channels. the double- length lines hop across every other clb to reduce the propagation delays in speed-critical nets. regenerating the signal strength is recommended after traversing three or four such segments. xact place-and-route software automatically connects buffers in the path of the signal as necessary. single- and double-length lines cannot drive onto longlines and global lines; longlines and global lines can, however, drive onto single- and double-length lines. as a general rule, longline and global-line connections to the programmable routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. longlines longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. row and column splitter pips in the middle of the array effectively double the total number of longlines by electrically dividing them into two separated half-lines. the horizontal longlines are driven by the 3-state buffers in each clb, and are driven by similar buffers at the periphery of the array from the versaring i/o interface. bus-oriented microprocessor designs are accommodated by using horizontal longlines in conjunction with the 3- state buffers in the clb and in the versaring. additionally, programmable keeper cells at the periphery can be enabled to retain the last valid logic level on the longlines when all buffers are in 3-state mode. longlines connect to the single-length or double-length lines, or to the logic inside the clb, through the general routing matrix. the only manner in which a longline can be driven is through the four 3-state buffers; therefore, a longline-to-longline or single-line-to-longline connection through pips in the general routing matrix is not possible. again, as a general rule, long- and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. the xc5200 family has no pull-ups on the ends of the longlines sourced by tbufs. consequently, wired functions (i.e., wand and worand) and wide multiplexing functions requiring pull-ups for unde?ned states (i.e., bus applications) must be implemented in a different way. in the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. in the case of 3-state bus applications, the user must insure that all states of the multiplexing function are de?ned. this process is as simple as adding an additional tbuf to drive the bus high when the previously unde?ned states are activated. global clock buffers global buffers in xilinx fpgas are special buffers that drive a dedicated routing network called global lines, as shown in figure 12. this network is intended for high-fan- out clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads. the xc5200 family has a total of four global buffers (bufg symbol in the library), each with its own dedicated routing channel. two are distributed vertically and two horizontally throughout the lca.
r 15 figure 11. xc5200 interconnect structure x4963 versa- block grm single-length lines double-length lines direct connects longlines and global lines 1 six levels of routing hierarchy 1 2 3 4 5 2 3 4 versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm local interconnect matrix logic cell feedthrough path (contained within each logic cell) lim 5 6 clb direct connects ts lim 4 4 4 4 4 lc3 lc2 lc1 lc0 4 4 44 24 24 6 grm
xc5200 logic cell array family preliminary 16 global lines two pairs of horizontal and vertical global lines provide low-skew clock signals to the clbs. global lines are driven by low-skew buffers inside the versaring. the global lines provide direct input only to the clb clock pins. the global lines also connect to the general routing matrix to provide access from these lines to the function generators and other control signals. four clock input pads at the corners of the chip, as shown in figure 12, provide a high-speed, low-skew clock network to each of the four global-line buffers. in addition to the dedicated pad, the global lines can be sourced by internal logic. pips from several routing channels within the versaring, inside the ioi cell, can also be con?gured to drive the global-line buffers. versaring input/output interface the versaring, shown in figure 13, is positioned between the core logic and the pad ring; it has all the routing resources of a versablock without the clb logic. the versaring decouples the pad rings pitch from the cores pitch. each versaring cell provides up to four pad-cell connections on one side, and connects directly to the clb ports on the other side. depending on placement and pad- cell pitch, any number of pad cells to a maximum of four can be connected to a versaring cell. note: there are no direct connects from the pads on top and bottom edges. input/output pad the i/o pad, shown in figure 14, consists of an input buffer and an output buffer. the output driver is an 8-ma full-rail cmos buffer with 3-state control. two slew-rate control modes are supported to minimize bus transients. both the output buffer and the 3-state control are invertible. figure 12. global lines gck1 gck4 gck3 gck2 x5704 the input buffer has globally selected cmos and ttl input thresholds. the input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set-up and hold times. minimum esd protection is 5 kv using the human body model. figure 13. versaring i/o interface figure 14. xc5200 i/o block 8 8 grm versablock 8 versaring 2 4 8 8 4 4 4 10 2 grm versablock 8 2 2 2 2 2 2 8 10 interconnect interconnect pad pad pad pad pad pad pad pad x5705 i o t pad vcc x4964
r 17 table 5. con?guration modes mode m2 m1 m0 cclk data master serial 0 0 0 output bit-serial slave serial 1 1 1 input bit-serial master parallel up 1 0 0 output byte-wide, 00000 - master parallel down 1 1 0 output byte-wide, 3ffff peripheral synchronous * 0 1 1 input byte-wide peripheral asynchronous 1 0 1 output byte-wide express 0 1 0 input byte-wide reserved 001 * peripheral synchronous can be considered byte-wide slave parallel con?guration con?guration is the process of loading design-speci?c programming data into one or more lca devices to de?ne the functional operation of the internal blocks and their interconnections. this is somewhat like loading the command registers of a programmable peripheral chip. each con?guration bit de?nes the state of a static memory cell that controls either a function lut bit, a multiplexer input, or an interconnect pass transistor. the xact development system translates the design into a netlist ?le. it automatically partitions, places, and routes the logic and generates the con?guration data in prom format. modes the xc5200 family has seven modes of con?guration, selected by a 3-bit input code applied to the lca mode pins (m0, m1, and m2). there are three self-clocking master modes, two peripheral modes, a slave serial mode, and a new high-speed slave parallel mode called the express. see table 5. brief descriptions of the seven modes are provided below. for details on all modes except express, see pages 2-32 through 2-41 of the 1994 xilinx programmable logic data book. master modes the master modes use an internal oscillator to generate cclk for driving potential slave devices, and to generate address and timing for external prom(s) containing the con?guration data. master parallel (up or down) modes generate the cclk signal and prom addresses, and receive byte parallel data, which is internally serialized into the lca data-frame format. the up and down selection generates starting addresses at either zero or 3ffff, to be compatible with different microprocessor addressing conventions. the master serial mode generates cclk and receives the con?guration data in serial form from con?guration data in serial form from a xilinx serial-con?guration prom. peripheral modes the two peripheral modes accept byte-wide data from a bus. a ready/busy status is available as a handshake signal. in the asynchronous mode, the internal oscillator generates a cclk burst signal that serializes the byte- wide data. in the synchronous mode, an externally supplied clock input to cclk serializes the data. slave serial mode in the slave serial mode, the lca device receives serial- con?guration data on the rising edge of cclk and, after loading its con?guration, passes additional data out, resynchronized on the next falling edge of cclk. multiple slave devices with identical con?gurations can be wired with parallel din inputs so that the devices can be con?gured simultaneously. daisy chaining multiple devices may be daisy-chained together so that they may be programmed using a single bitstream. the ?rst device in the chain may be set to operate in any mode. all devices except the ?rst device in the chain must be set to operate in slave serial mode. all cclk pins are tied together and the data chain passes from dout to din of successive devices along the chain.
xc5200 logic cell array family preliminary 18 express mode the express mode (see figure 15) is similar to the slave serial mode, except that data is processed one byte per cclk cycle instead of one bit per cclk cycle. an external source is used to drive cclk while byte-wide data is loaded directly into the con?guration data shift registers. in this mode the xc5200 family is capable of supporting a cclk frequency of 10 mhz, which is equivalent to an 80-mhz serial rate, because eight bits of con?guration data are being loaded per cclk cycle. an xc5210 in the express mode, for instance, can be con?gured in about 2 ms. the express mode does not support crc error checking, but does support constant- ?eld error checking. in the express con?guration mode, an external signal drives the cclk input(s) of the lca device(s). the ?rst bytes of parallel con?guration data must be available at the d inputs of the lca devices a short set-up time before each rising cclk edge. subsequent data bytes are clocked in on each consecutive rising cclk edge. see figure 16. the express mode is only supported by the xc5200 family. it may not be used, therefore, when an xc5200 device is daisy-chained with devices from other xilinx families. if the ?rst device is con?gured in the express mode, additional devices may be daisy-chained only if every device in the chain is also con?gured in the express mode. cclk pins are tied together and d7-d0 pins are tied together for all devices along the chain. a status signal is passed from dout to cs1 of successive devices along the chain. the lead device in the chain has its cs1 input tied high (or ?oating, since there is an internal pull- up). all devices receive and recognize the preamble and length count, but frame data is accepted only when cs1 is high and the devices con?guration memory is not already full. the status pin dout is pulled low two internal- oscillator cycles (nominally 1 mhz per cycle) after init is recognized as high, and remains low until the devices con?guration memory is full. then dout is pulled high to signal the next device in the chain to accept the con?guration data on the d7-d0 bus. how to delay con?guration after power-up for details on how to delay con?guration after power-up, refer to page 2-32 of the 1994 xilinx programmable logic data book. figure 15. express mode init cclk cclk xc5200 m0 m1 m2 cs1 d0-d7 data bus program init cclk program init dout dout to additional optional daisy-chained devices to additional optional daisy-chained devices optional daisy-chained xc5200 m0 m1 +5v 5k +5v m2 cs1 d0-d7 program x6153
r 19 figure 16. express mode programming switching characteristics x6154 byte 0 cclk lca filled 1 2 3 init t dc t cd t ic d0-d7 serial data out (dout) rdy/busy cs1 byte 1 byte 2 byte 3 internal init description symbol min max units cclk init (high) setup time required 1 t ic 5 m s din setup time required 2 t dc 50 ns din hold time required 3 t cd 0 ns cclk high time t cch 50 ns cclk low time t ccl 50 ns cclk frequency f cc 10 mhz preliminary format table 6 describes the xc5200 con?guration data stream. table 7 provides details of the internal con?guration data structure. con?guration sequence figure 17 illustrates the xc5200 start-up sequence. it is described in detail in the sections below. clear internal logic when reprogramming the xc5200 chip, a contention-free state must be reached before memory initialization can begin. in this state internal control lines sequence activities in the following order: long lines are disabled, output drivers are forced low, and interconnect lines are discharged. each of these operations requires one cycle of the 1-mhz initialization clock. this sequencing is important only when reprogramming, because the contention-free state is immediately entered when con?guring from a power-on state.
xc5200 logic cell array family preliminary 20 table 6. uni?ed xc5200 bitstream format data type value fill byte 11111111 preamble 11110010 length counter count(23:0) fill byte 11111111 start byte 11111110 data frame * data(n-1:0) cyclic redundancy check or constant field check crc(3:0) or 0110 fill nibble 1111 extend write cycle ffffff postamble 11111110 fill bytes (30) ffffff legend: (unshaded) only once per bitstream (light) once per data frame (dark) once per device table 7. internal con?guration data structure device versablock array prom size (bits) xilinx serial prom needed xc5202 8 x 8 42,448 xc1765 xc5204 10 x 12 70,736 xc1728 xc5206 14 x 14 106,320 xc17128 xc5210 18 x 18 165,520 xc17256 xc5215 22 x 22 237,776 xc17256 bits per frame = (34 x number of rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 8 error check bits + 4 ?ll bits + 4 extended write bits number of frames = (12 x number of columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit program data = (bits per frame x number of frames) + 48 header bits + 8 postamble bits + 280 ?ll bits prom size = program data figure 17. start-up sequence init high? if master sample mode lines load one configuration data frame frame error pass configuration data to dout v cc 3v no yes yes no no yes operational start-up sequence no yes ~1.3 m s per frame master cclk goes active after 50 to 250 s f pull init low and stop x6037 extest* sample/preload* bypass configure* (*only when program = high) sample/preload bypass extest sample preload bypass user 1 user 2 configure readback if boundary scan is selected config- uration memory full cclk count equals length count completely clear configuration memory ldc output = l, hdc output = h boundary scan instructions available: i/o active generate one time-out pulse of 4 ms program = low no yes yes
r 21 clear address registers during this phase the con?guration address registers are cleared to ensure that they will contain at most a single token at all times. prior to memory initialization, the xc5200 device eliminates the possibility of multiple tokens within the address register, as is typically the case when powering on. power-on time-out an internal power-on reset circuit is triggered when power is applied. when v cc reaches the voltage at which portions of the lca begin to operate (i.e., performs a write-and-read test of a sample pair of con?guration memory bits), the programmable i/o buffers are 3-stated with active high-impedance pull-up resistors. a time-out delay nominally 4 ms is initiated to allow the power- supply voltage to stabilize. for correct operation the power supply must reach v cc (min) by the end of the time- out, and must not dip below it thereafter. there is no distinction between master and slave modes with regard to the time-out delay. instead, the init line is used to ensure that all daisy-chained devices have completed initialization. since xc2000 devices do not have this signal, extra care must be taken to guarantee proper operation when daisy-chaining them with xc5200 devices. for proper operation with xc3000 devices, the reset signal, which is used in xc3000 to delay con?guration, should be connected to init. if the time-out delay is insuf?cient, con?guration should be delayed by holding the init pin low until the power supply has reached operating levels. during all three phases power-on, initialization, and con?guration done is held low; hdc, ldc, and init are active; dout is driven; and all i/o buffers are disabled. initialization this phase clears the con?guration memory and establishes the con?guration mode. the con?guration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 mhz). an open- drain bidirectional signal, init, is released when the con?guration memory is completely cleared. the device then tests for the absence of an external active-low level on init. the mode lines are sampled two internal clock cycles later (nominally 2 m s). the master device waits an additional 32 m s to 256 m s (nominally 64-128 m s) to provide adequate time for all of the slave devices to recognize the release of init as well. then the master device enters the con?guration phase. con?guration the length counter begins counting immediately upon entry into the con?guration state. in slave-mode operation it is important to wait at least two cycles of the internal 1-mhz clock oscillator after init is recognized before toggling cclk and feeding the serial bitstream. con?guration will not begin until the internal con?guration logic reset is released, which happens two cycles after init goes high. a master devices con?guration is delayed from 32 to 256 m s to ensure proper operation with any slave devices driven by the master device. a preamble ?eld at the beginning of the con?guration data stream indicates that the next 24 bits represent the length count. the length count equals the total number of con?guration bits needed to load the complete con?guration data to all daisy-chained devices. once the preamble and length-count values have been passed through to the next device in the daisy-chain, dout is held high to prevent start bits from reaching any daisy- chained devices. after fully con?guring itself, the device passes serial data to downstream daisy-chained devices via dout until the full length count is reached. errors in the con?guration bitstream are checked at the end of a frame of data. the device does not check the preamble or length count for errors. in a daisy-chained con?guration, con?guration data for downstream devices are not checked for errors. if an error is detected after reading a frame, the err pin (also known as init) is immediately pulled low and all con?guration activity ceases. however, a master or peripheral asynchronous device will continue outputting a con?guration clock and incrementing the prom address inde?nitely even though it will never complete con?guration. a reprogram or power-on must be applied to remove the device from this state. start-up and operation the xc5200 start-up sequence is identical to that of the xc4000 family. each of these events may occur in any order: (a) done is pulled high; and/or (b) user i/os become active; and/or (c) internal reset is deactivated. as a con?guration option, the three events may be triggered by a user clock rather than by cclk, or the start- up sequence may be delayed by externally holding the done pin low. in any mode, the clock cycles of the start-up sequence hare not included in the length count. the length of the bitstream is greater than the length count.
xc5200 logic cell array family preliminary 22 pin functions during con?guration before and during con?guration, all outputs that are not used for the con?guration process are 3-stated with a 50-k w to 100-k w pull-up resistor. configuration mode: user operation slave <1:1:1> master-ser <0:0:0> syn.periph <0:1:1> asyn.periph <1:0:1> master-high <1:1:0> master-low <1:0:0> a16 a16 gck1-i/o a17 a17 i/o tdi tdi tdi tdi tdi tdi tdi-i/o tck tck tck tck tck tck tck-i/o tms tms tms tms tms tms tms-i/o i/o m1 (high) (i) m1 (low) (i) m1 (high) (i) m1 (low) (i) m1 (high) (i) m1 (low) (i) i/o m0 (high) (i) m0 (low) (i) m0 (high) (i) m0 (high) (i) m0 (low) (i) m0 (low) (i) i/o m2 (high) (i) m2 (low) (i) m2 (low) (i) m2 (high) (i) m2 (high) (i) m2 (high) (i) i/o gck2-i/o hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) i/o ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) i/o init- error init- error init- error init- error init- error init- error i/o i/o done done done done done done done program (i) program (i) program (i) program (i) program (i) program (i) program data 7 (i) data 7 (i) data 7 (i) data 7 (i) i/o gck3-i/o data 6 (i) data 6 (i) data 6 (i) data 6 (i) i/o data 5 (i) data 5 (i) data 5 (i) data 5 (i) i/o cso (i) i/o data 4 (i) data 4 (i) data 4 (i) data 4 (i) i/o data 3 (i) data 3 (i) data 3 (i) data 3 (i) i/o rs (i) i/o data 2 (i) data 2 (i) data 2 (i) data 2 (i) i/o data 1 (i) data 1 (i) data 1 (i) data 1 (i) i/o rdy/ busy rdy/ busy rclk rclk i/o din (i) din (i) data 0 (i) data 0 (i) data 0 (i) data 0 (i) i/o dout dout dout dout dout dout i/o cclk (i) cclk (o) cclk (i) cclk (o) cclk (o) cclk (o) cclk (i) tdo tdo tdo tdo tdo tdo tdo-i/o ws (i) a0 a0 i/o a1 a1 gck4-i/o cs1 (i) a2 a2 i/o a3 a3 i/o a4 a4 i/o a5 a5 i/o a6 a6 i/o a7 a7 i/o a8 a8 i/o a9 a9 i/o a10 a10 i/o a11 a11 i/o a12 a12 i/o a13 a13 i/o a14 a14 i/o a15 a15 i/o all others represents a 50-k w to 100-k w pull-up before and during con?guration * init is an open-drain output during con?guration (i) represents an input (o) represents an output
r 23 permanently dedicated pins v cc eight or more (depending on package type) connections to the nominal +5-v supply voltage. all must be connected. gnd eight or more (depending on package type) connections to ground. all must be connected. cclk during con?guration, con?guration clock is an output of the lca in master modes or asynchronous peripheral mode, but is an input to the lca in slave serial mode and synchronous peripheral mode. after con?guration, cclk has a weak pull-up resistor and can be selected as readback clock. done this is a bidirectional signal with optional pull-up resistor. as an output, it indicates the completion of the con?guration process. the con?guration program determines the exact timing, the clock source for the low- to-high transition, and enable of the pull-up resistor. as an input, a low level on done can be con?gured to delay the global logic initialization or the enabling of outputs. program this is an active-low input, held low during con?guration, that forces the lca to clear its con?guration memory. when program goes high, the lca executes a complete clear cycle, before it goes into a wait state and releases init. after con?guration, it has an optional pull- up resistor. user i/o pins that can have special functions rdy/ busy during peripheral modes, this pin indicates when it is appropriate to write another byte of data into the lca device. the same status is also available on d7 in asynchronous peripheral mode, if a read operation is performed when the device is selected. after con?guration, this is a user-programmable i/o pin. rclk during master parallel con?guration, each change on the a0-15 outputs is preceded by a rising edge on rclk, a redundant output signal. after con?guration, this is a user- programmable i/o pin. m0, m1, m2 as mode inputs, these pins are sampled before the start of con?guration to determine the con?guration mode to be used. after con?guration, m0, m1, and m2 become user- programmable i/o. tdo if boundary scan is used, this is the test data output. if boundary scan is not used, this pin becomes user- programmable i/o. tdi, tck, tms if boundary scan is used, these pins are test data in, test clock, and test mode select inputs, respectively, coming directly from the pads, bypassing the iobs. these pins can also be used as inputs to the clb logic after con?guration is completed. if the boundary scan option is not selected, all boundary scan functions are inhibited once con?guration is completed. these pins become user-programmable i/o. hdc high during con?guration is driven high until con?guration is completed. it is available as a control output indicating that con?guration is not yet completed. after con?guration, this is a user-programmable i/o pin. pin descriptions
xc5200 logic cell array family preliminary 24 ldc low during con?guration is driven low until con?guration completes. it is available as a control output indicating that con?guration is not yet completed. after con?guration, this is a user-programmable i/o pin. init before and during con?guration, this is a bidirectional signal. an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during the power stabilization and internal clearing of the con?guration memory. as an active-low input, it can be used to hold the lca device in the internal wait state before the start of con?guration. master-mode devices stay in a wait state an additional 30 to 300 m s after init has gone high. during con?guration, a low on this output indicates that a con?guration data error has occurred. after con?guration, this is a user-programmable i/o pin. gck1 - gck4 four global inputs each drive a dedicated internal global net with short delay and minimal skew. if not used for this purpose, any of these pins is a user-programmable i/o pin. cs0, cs1, ws, rs these four inputs are used in peripheral modes. the chip is selected when cs0 is low and cs1 is high. while the chip is selected, a low on write strobe ( ws) loads the data present on the d0 - d7 inputs into the internal data buffer; a low on read strobe ( rs) changes d7 into a status output: high if ready, low if busy, and d0d6 are active low. ws and rs should be mutually exclusive, but if both are low simultaneously, the write strobe overrides. after con?guration, these are user-programmable i/o pins. a0 - a17 during master parallel mode, these 18 output pins address the con?guration eprom. after con?guration, these are user-programmable i/o pins. d0 - d7 during master parallel and peripheral con?guration modes, these eight input pins receive con?guration data. after con?guration, they are user-programmable i/o pins. din during slave serial or master serial con?guration modes, this is the serial con?guration data input receiving data on the rising edge of cclk. during parallel con?guration modes, this is the d0 input. after con?guration, din is a user-programmable i/o pin. dout during con?guration in any mode, this is the serial con?guration data output that can drive the din of daisy- chained slave lca devices. dout data changes on the falling edge of cclk, 1.5 cclk periods after it was received at the din input. after con?guration, dout is a user-programmable i/o pins. unrestricted user-programmable i/o pins i/o a pin that can be con?gured to be input and/or output after con?guration is completed. before con?guration is completed, these pins have an internal high-value pull-up resistor that de?nes the logical level as high. pin descriptions before and during con?guration, all outputs that are not used for the con?guration process are 3-stated with a 50-k w to 100-k w pull-up resistor.
r 25 absolute maximum ratings operating conditions dc characteristics over operating conditions symbol description units v cc supply voltage relative to gnd -0.5 to +7.0 v v in input voltage with respect to gnd -0.5 to v cc +0.5 v v ts voltage applied to 3-state output -0.5 to v cc +0.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature in plastic packages +125 c junction temperature in ceramic packages +150 c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc supply voltage relative to gnd commercial: 0 c to 70 c 4.75 5.25 v supply voltage relative to gnd industrial: -40 c to 85 c 4.5 5.5 v supply voltage relative to gnd military: -55 c to 125 c 4.5 5.5 v v iht high-level input voltage ttl con?guration 2.0 v cc v v ilt low-level input voltage ttl con?guration 0 0.8 v v ihc high-level input voltage cmos con?guration 70% 100% v cc v ilc low-level input voltage cmos con?guration 0 20% v cc t in input signal transition time 250 ns symbol description min max units v oh high-level output voltage @ i oh = -8.0 ma, v cc min 3.86 v v ol low-level output voltage @ i ol = 8.0 ma, v cc max (note 1) 0.4 v i cco quiescent lca supply current (note 1) 15 ma i il leakage current -10 +10 m a c in input capacitance (sample tested) 15 pf i rin pad pull-up (when selected) @ v in = 0v (sample tested) 0.02 0.25 ma note: 1. with no output current loads, all package pins at v cc or gnd, and the lca con?gured with a makebits tie option.
xc5200 logic cell array family preliminary 26 global buffer switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines re?ect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the xact timing calculator and used in the simulator. speed grade -6 -5 -4 description symbol device max (ns) max (ns) max (ns) global signal distribution from pad through global buffer, to any clock (ck) t bufg xc5202 xc5204 xc5206 9.4 8.8 xc5210 9.4 8.8 xc5215 internal clock to output pad delay from clock (ck) to output pad (fast), using direct connect between q and output (o) t okpof xc5202 xc5204 xc5206 9.9 8.9 xc5210 9.9 8.9 xc5215 from clock (ck) to output pad (slew-limited), using direct connect between q and output (o) t okpos xc5202 xc5204 xc5206 14.8 12.7 xc5210 14.8 12.7 xc5215 note: 1. die-size-dependent parameters are based upon xc5210 characterization. production speci?cations will vary with array size.
r 27 longline switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines re?ect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the xact timing calculator and used in the simulator. speed grade -6 -5 -4 description symbol device max (ns) max (ns) max (ns) tbuf driving a longline i to longline, while ts is low; i.e., buffer is constantly active t io xc5202 xc5204 xc5206 4.0 3.6 xc5210 4.0 3.6 xc5215 ts going low to longline going from ?oating high or low to active low or high t on xc5202 xc5204 xc5206 5.3 4.8 xc5210 5.3 4.8 xc5215 ts going high to tbuf going inactive, not driving longline t off xc5202 xc5204 xc5206 2.4 2.2 xc5210 2.4 2.2 xc5215 note: 1. die-size-dependent parameters are based upon xc5210 characterization. production speci?cations will vary with array size. ts io tbuf
xc5200 logic cell array family preliminary 28 guaranteed input and output parameters (pin-to-pin) all values listed below are tested directly, and guaranteed over the operating conditions. the same parameters can also be derived indirectly from the global buffer speci?cations. the xact delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. when there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. speed grade -6 -5 -4 description symbol device max (ns) max (ns) max (ns) global clock to output pad (fast) t ickof (max) xc5202 xc5204 xc5206 17.2 15.4 xc5210 17.2 15.4 xc5215 global clock to output pad (slew-limited) t icko (max) xc5202 xc5204 xc5206 21.7 19.0 xc5210 21.7 19.0 xc5215 input set-up time (no delay) to clb flip-flop t psuf (min) xc5202 xc5204 xc5206 1.2 0.5 xc5210 1.2 0.5 xc5215 input hold time (no delay) to clb flip-flop t phf (min) xc5202 xc5204 xc5206 3.0 2.5 xc5210 3.0 2.5 xc5215 input set-up time (with delay) to clb flip-flop t psu (min) xc5202 xc5204 xc5206 7.5 6.4 xc5210 7.5 6.4 xc5215 input hold time (with delay) to clb flip-flop t ph (min) xc5202 xc5204 xc5206 00 xc5210 00 xc5215 note: 1. these measurements assume that the ?ip-?op has a direct connect to or from the iob. xact-performance can be used to assure that direct connects are used. 2. when testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. 3. die-size-dependent parameters are based upon xc5210 characterization. production speci?cations will vary with array size. global clock-to-output delay fd . . . . t bufg direct connect iob clb global clock-to-output delay fd . . . . t bufg direct connect iob clb input set-up & hold time fd t bufg iob direct connect clb input set-up & hold time fd t bufg iob direct connect clb input set-up & hold time fd t bufg iob direct connect clb input set-up & hold time fd t bufg iob direct connect clb
r 29 iob switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines re?ect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the xact timing calculator and used in the simulator. speed grade -6 -5 -4 description symbol max (ns) max (ns) max (ns) input propagation delays from cmos or ttl levels pad to i (no delay) t pi 5.4 4.9 pad to i (with delay) t pid 11.1 10.2 output propagation delays to cmos or ttl levels output (o) to pad (fast) t opf 4.6 4.5 output (o) to pad (slew-limited) t ops 9.4 8.3 3-state to pad active (fast) t tsonf 6.9 6.6 3-state to pad active (slew-limited) t tsons 11.6 10.4 internal gts to pad active (fast) t gtsf 17.7 15.9 internal gts to pad active (slew-limited) t gtss 22.3 19.7 note: 1. timing is measured at pin threshold, with 50-pf external capacitance loads. slew-limited output rise/fall times are approximately two times longer than fast output rise/fall times. for the effect of capacitive loads on ground bounce, see pages 8-8 through 8-10 of the 1994 xilinx programmable logic data book. 2. unused and unbonded iobs are con?gured by default as inputs with internal pull-up resistors.
xc5200 logic cell array family preliminary 30 clb switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines re?ect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the xact timing calculator and used in the simulator. speed grade -6 -5 -4 description symbol min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) combinatorial delays f inputs to x output t ilo 5.5 4.5 di inputs to do output (logic-cell feedthrough) t ido 4.2 3.3 f inputs via f5_mux to do output t imo 7.1 5.7 carry delays incremental delay per bit t cy 0.7 0.6 carry-in overhead from di t cydi 1.7 1.5 carry-in overhead from f t cyl 3.6 3.2 carry-out overhead to do t cyo 3.9 3.1 sequential delays clock (ck) to out (q) (flip-flop) t cko 5.4 4.4 gate (latch enable) going active to out (q) t go 8.6 6.8 set-up time before clock (ck) f inputs t ick 2.1 1.5 f inputs via f5_mux t mick 3.6 2.7 di input t dick 0.5 0.3 ce input t eick 1.2 0.9 hold times after clock (ck) f inputs t cki 00 f inputs via f5_mux t ckmi 00 di input t ckdi 00 ce input t ckei 00 clock widths clock high time t ch 6.0 6.0 clock low time t cl 6.0 6.0 reset delays width (high) t clrw 6.0 6.0 delay from clr to q (flip-flop) t clr 7.3 5.8 delay from clr to q (latch) t clrl 6.1 4.8 global reset delays (see note 2) width (high) t gclrw 6.0 6.0 delay from internal gclr to q t gclr 12.4 10.2 note: 1. the clb k to q output delay (t cko ) of any clb, plus the shortest possible interconnect delay, is always longer than the data in hold-time requirement (t ckdi ) of any clb on the same die. 2. timing is based upon the xc5210 device. for other devices, see xact timing calculator.
r 31
xc5200 logic cell array family preliminary (v1.0) 32 figure 18. xc5206 clb-to-pad relationship r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c11 r1c12 r1c13 r1c14 r2c1 r3c1 r4c1 r5c1 r6c1 r7c1 r8c1 r9c1 r10c1 r11c1 r12c1 r13c1 r14c1 clb, identified by r#c# = row and column numbers i/o pad r#c# key: top bottom right left r14c2 r14c3 r14c4 r14c5 r14c6 r14c7 r14c8 r14c9 r14c10 r14c11 r14c12 r14c13 r14c14 r2c14 r3c14 r4c14 r5c14 r6c14 r7c14 r8c14 r9c14 r10c14 r11c14 r12c14 r13c14
r 33 figure 19. xc5206 clb-to-pad relationship (detail) note: pad numbers (1, 2, , 148) refer to die pads, not external device pins. also see the xc5206 pinout table on pages 36-37. r2c1 r3c1 r4c1 r5c1 r6c1 r7c1 r8c1 r9c1 r10c1 r11c1 r12c1 r13c1 r14c1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 r14c2 r14c3 r14c4 r14c5 r14c6 r14c7 r14c8 r14c9 r14c10 r14c11 r14c12 r14c13 r14c14 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 r2c14 r3c14 r4c14 r5c14 r6c14 r7c14 r8c14 r9c14 r10c14 r11c14 r12c14 r13c14 r14c14 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c11 r1c12 r1c13 r1c14 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 r1c1 r14c1 r1c14 left bottom right top
xc5200 logic cell array family preliminary (v1.0) 34 figure 20. xc5210 clb-to-pad relationship r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c11 r1c12 r1c13 r1c14 r2c1 r3c1 r4c1 r5c1 r6c1 r7c1 r8c1 r9c1 r10c1 r11c1 r12c1 r13c1 r14c1 r1c15 r1c16 r1c17 r1c18 r15c1 r16c1 r17c1 r18c1 r2c18 r3c18 r4c18 r5c18 r6c18 r7c18 r8c18 r9c18 r10c18 r11c18 r12c18 r13c18 r14c18 r15c18 r16c18 r17c18 r18c18 r18c2 r18c3 r18c4 r18c5 r18c6 r18c7 r18c8 r18c9 r18c10 r18c11 r18c12 r18c13 r18c14 r18c15 r18c16 r18c17 clb, identified by r#c# = row and column numbers i/o pad r#c# key: top bottom right left
r 35 figure 21. xc5210 clb-to-pad relationship (detail) r2c1 r3c1 r4c1 r5c1 r6c1 r7c1 r8c1 r9c1 r10c1 r11c1 r12c1 r13c1 r14c1 r15c1 r16c1 r17c1 r18c1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 r18c2 r18c3 r18c4 r18c5 r18c6 r18c7 r18c8 r18c9 r18c10 r18c11 r18c12 r18c13 r18c14 r18c15 r18c16 r18c17 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 r2c18 r3c18 r4c18 r5c18 r6c18 r7c18 r8c18 r9c18 r10c18 r11c18 r12c18 r13c18 r14c18 r15c18 r16c18 r17c18 r18c18 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c11 r1c12 r1c13 r1c14 r1c15 r1c16 r1c17 r1c18 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 r1c1 r18c1 r18c18 r1c18 left bottom right top note: pad numbers (1, 2, , 196) refer to die pads, not external device pins. also see the xc5210 pinout table on pages 38-39.
xc5200 logic cell array family preliminary (v1.0) 36 pin description ? pc84 pq160 pq208 pg191 boundary scan order vcc 2 142 183 j4 - 1. i/o (a8) 3 143 184 j3 87 2. i/o (a9) 4 144 185 j2 90 3. i/o - 145 186 j1 93 4. i/o - 146 187 h1 99 5. i/o - - 188 h2 102 6. i/o - - 189 h3 105 7. i/o (a10) 5 147 190 g1 111 8. i/o (a11) 6 148 191 g2 114 9. i/o - 149 192 f1 117 10. i/o - 150 193 e1 123 gnd - 151 194 g3 - - - - 195* - - - - - 196* - - 11. i/o - 152 197 c1 126 12. i/o - 153 198 e2 129 13. i/o (a12) 7 154 199 f3 138 14. i/o (a13) 8 155 200 d2 141 15. i/o - 156 201 b1 150 16. i/o - 157 202 e3 153 17. i/o (a14) 9 158 203 c2 162 18. i/o (a15) 10 159 204 b2 165 vcc 11 160 205 d3 - - - - 206* - - - - - 207* - - - - - 208* - - ---1*-- gnd 12 1 2 d4 - ---3*-- 19. gck1 (a16, i/o) 13 2 4 c3 174 20. i/o (a17) 14 3 5 c4 177 21. i/o - 4 6 b3 183 22. i/o - 5 7 c5 186 23. i/o (tdi) 15 6 8 a2 189 24. i/o (tck) 16 7 9 b4 195 25. i/o - 8 10 c6 198 26. i/o - 9 11 a3 201 - - - 12* - - - - - 13* - - gnd -1014c7 - 27. i/o - 11 15 a4 207 28. i/o - 12 16 a5 210 29. i/o (tms) 17 13 17 b7 213 30. i/o 18 14 18 a6 219 31. i/o - - 19 c8 222 32. i/o - - 20 a7 225 33. i/o - 15 21 b8 234 34. i/o - 16 22 a8 237 35. i/o 19 17 23 b9 246 36. i/o 20 18 24 c9 249 gnd 21 19 25 d9 - vcc 22 20 26 d10 - 37. i/o 23 21 27 c10 255 38. i/o 24 22 28 b10 258 39. i/o - 23 29 a9 261 40. i/o - 24 30 a10 267 41. i/o - - 31 a11 270 42. i/o - - 32 c11 273 43. i/o 25 25 33 b11 279 44. i/o 26 26 34 a12 282 45. i/o - 27 35 b12 285 46. i/o - 28 36 a13 291 gnd - 29 37 c12 - - - - 38* - - - - - 39* - - 47. i/o - 30 40 a15 294 48. i/o - 31 41 c13 297 49. i/o 27 32 42 b14 303 50. i/o - 33 43 a16 306 51. i/o - 34 44 b15 309 52. i/o - 35 45 c14 315 53. i/o 28 36 46 a17 318 54. i/o 29 37 47 b16 321 55. m1 (i/o) 30 38 48 c15 330 gnd 31 39 49 d15 - 56. m0 (i/o) 32 40 50 a18 333 - - - 51* - - - - - 52* - - - - - 53* - - - - - 54* - - vcc 33 41 55 d16 - 57. m2 (i/o) 34 42 56 c16 336 58. gck2 (i/o) 35 43 57 b17 339 59. i/o (hdc) 36 44 58 e16 348 60. i/o - 45 59 c17 351 61. i/o - 46 60 d17 354 62. i/o - 47 61 b18 360 63. i/o (ldc) 37 48 62 e17 363 64. i/o - 49 63 f16 372 65. i/o - 50 64 c18 375 gnd - 51 67 g16 - 66. i/o - 52 68 e18 378 67. i/o - 53 69 f18 384 68. i/o 38 54 70 g17 387 69. i/o 39 55 71 g18 390 70. i/o - - 72 h16 396 71. i/o - - 73 h17 399 72. i/o - 56 74 h18 402 73. i/o - 57 75 j18 408 74. i/o 40 58 76 j17 411 75. i/o ( err, init) 41 59 77 j16 414 vcc 42 60 78 j15 - gnd 43 61 79 k15 - 76. i/o 44 62 80 k16 420 pin description ? pc84 pq160 pq208 pg191 boundary scan order xc5206 pinouts * indicates unconnected package pins. ? leading number refers to bonded pad, shown in figure 19.
r 37 xc5206 pinouts (continued) 77. i/o 45 63 81 k17 423 78. i/o - 64 82 k18 426 79. i/o - 65 83 l18 432 80. i/o - - 84 l17 435 81. i/o - - 85 l16 438 82. i/o 46 66 86 m18 444 83. i/o 47 67 87 m17 447 84. i/o - 68 88 n18 450 85. i/o - 69 89 p18 456 gnd - 70 90 m16 - - - - 91* - - - - - 92* - - 86. i/o - 71 93 t18 459 87. i/o - 72 94 p17 468 88. i/o 48 73 95 n16 471 89. i/o 49 74 96 t17 480 90. i/o - 75 97 r17 483 91. i/o - 76 98 p16 486 92. i/o 50 77 99 u18 492 93. i/o 51 78 100 t16 495 gnd 52 79 101 r16 - - - - 102* - - done 53 80 103 u17 - - - - 104* - - - - - 105* - - vcc 54 81 106 r15 - - - - 107* - - prog 55 82 108 v18 - 94. i/o (d7) 56 83 109 t15 504 95. gck3 (i/o) 57 84 110 u16 507 96. i/o - 85 111 t14 516 97. i/o - 86 112 u15 519 98. i/o (d6) 58 87 113 v17 522 99. i/o - 88 114 v16 528 100. i/o - 89 115 t13 531 101. i/o - 90 116 u14 534 - - - 117* - - - - - 118* - - gnd - 91 119 t12 - 102. i/o - 92 120 u13 540 103. i/o - 93 121 v13 543 104. i/o (d5) 59 94 122 u12 552 105. i/o ( cs0) 60 95 123 v12 555 106. i/o - - 124 t11 558 107. i/o - - 125 u11 564 108. i/o - 96 126 v11 567 109. i/o - 97 127 v10 570 110. i/o (d4) 61 98 128 u10 576 111. i/o 62 99 129 t10 579 vcc 63 100 130 r10 - gnd 64 101 131 r9 - pin description ? pc84 pq160 pq208 pg191 boundary scan order 112. i/o (d3) 65 102 132 t9 588 113. i/o ( rs) 66 103 133 u9 591 114. i/o - 104 134 v9 600 115. i/o - 105 135 v8 603 116. i/o - - 136 u8 612 117. i/o - - 137 t8 615 118. i/o (d2) 67 106 138 v7 618 119. i/o 68 107 139 u7 624 120. i/o - 108 140 v6 627 121. i/o - 109 141 u6 630 gnd - 110 142 t7 - - - - 143* - - - - - 144* - - 122. i/o - 111 145 u5 636 123. i/o - 112 146 t6 639 124. i/o (d1) 69 113 147 v3 642 125. i/o ( rclk- busy/rdy) 70 114 148 v2 648 126. i/o - 115 149 u4 651 127. i/o - 116 150 t5 654 128. i/o (d0, din) 71 117 151 u3 660 129. i/o (dout) 72 118 152 t4 663 cclk 73 119 153 v1 - vcc 74 120 154 r4 - - - - 155* - - - - - 156* - - - - - 157* - - - - - 158* - - 130. (i/o) tdo 75 121 159 u2 - gnd 76 122 160 r3 - 131. i/o (a0, ws) 77 123 161 t3 9 132. i/o (gck4, a1) 78 124 162 u1 15 133. i/o - 125 163 p3 18 134. i/o - 126 164 r2 21 135. i/o (cs1, a2) 79 127 165 t2 27 136. i/o (a3) 80 128 166 n3 30 137. i/o - 129 167 p2 33 138. i/o - 130 168 t1 42 - - - 169* - - - - - 170* - - gnd - 131 171 m3 - 139. i/o - 132 172 p1 45 140. i/o - 133 173 n1 51 141. i/o (a4) 81 134 174 m2 54 142. i/o (a5) 82 135 175 m1 57 143. i/o - - 176 l3 63 144. i/o - 136 177 l2 66 145. i/o - 137 178 l1 69 146. i/o - 138 179 k1 75 147. i/o (a6) 83 139 180 k2 78 148. i/o (a7) 84 140 181 k3 81 gnd 1 141 182 k4 - pin description ? pc84 pq160 pq208 pg191 boundary scan order boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 666 = bscan.upd
xc5200 logic cell array family preliminary (v1.0) 38 pin description ? pc84 pq160 pq208 pg223 pq240 boundary scan order vcc 2 142 183 j4 212 - 1. i/o (a8) 3 143 184 j3 213 111 2. i/o (a9) 4 144 185 j2 214 114 3. i/o - 145 186 j1 215 117 4. i/o - 146 187 h1 216 123 5. i/o - - 188 h2 217 126 6. i/o - - 189 h3 218 129 - - - - - 219* - 7. i/o (a10) 5 147 190 g1 220 135 8. i/o (a11) 6 148 191 g2 221 138 vcc - - - - 222 - 9. i/o - - - h4 223 141 10. i/o - - - g4 224 150 11. i/o - 149 192 f1 225 153 12. i/o - 150 193 e1 226 162 gnd - 151 194 g3 227 - 13. i/o - - 195 f2 228 165 14. i/o - - 196 d1 229 171 15. i/o - 152 197 c1 230 174 16. i/o - 153 198 e2 231 177 17. i/o (a12) 7 154 199 f3 232 183 18. i/o (a13) 8 155 200 d2 233 186 19. i/o - - - f4 234 189 20. i/o - - - e4 235 195 21. i/o - 156 201 b1 236 198 22. i/o - 157 202 e3 237 201 23. i/o (a14) 9 158 203 c2 238 210 24. i/o (a15) 10 159 204 b2 239 213 vcc 11 160 205 d3 240 - - - - 206* - - - - - - 207* - - - - - - 208* - - - - - -1*- - - gnd 12 1 2 d4 1 - - - -3*- - - 25. gck1 (a16, i/o) 13 2 4 c3 2 222 26. i/o (a17) 14 3 5 c4 3 225 27. i/o - 4 6 b3 4 231 28. i/o - 5 7 c5 5 234 29. i/o (tdi) 15 6 8 a2 6 237 30. i/o (tck) 16 7 9 b4 7 243 31. i/o - 8 10 c6 8 246 32. i/o - 9 11 a3 9 249 33. i/o - - 12 b5 10 255 34. i/o - - 13 b6 11 258 35. i/o - - - d5 12 261 36. i/o - - - d6 13 267 gnd - 1014c714 - 37. i/o - 11 15 a4 15 270 38. i/o - 12 16 a5 16 273 39. i/o (tms) 17 13 17 b7 17 279 40. i/o 18 14 18 a6 18 282 vcc - - - - 19 - 41. i/o - - - d7 20 285 42. i/o - - - d8 21 291 - - - - - 22* - 43. i/o - - 19 c8 23 294 44. i/o - - 20 a7 24 297 45. i/o - 15 21 b8 25 306 46. i/o - 16 22 a8 26 309 47. i/o 19 17 23 b9 27 318 48. i/o 20 18 24 c9 28 321 gnd 21 19 25 d9 29 - vcc 22 20 26 d10 30 - 49. i/o 23 21 27 c10 31 327 50. i/o 24 22 28 b10 32 330 51. i/o - 23 29 a9 33 333 52. i/o - 24 30 a10 34 339 53. i/o - - 31 a11 35 342 54. i/o - - 32 c11 36 345 - - - - - 37* - 55. i/o - - - d11 38 351 56. i/o - - - d12 39 354 vcc ----40 - 57. i/o 25 25 33 b11 41 357 58. i/o 26 26 34 a12 42 363 59. i/o - 27 35 b12 43 366 60. i/o - 28 36 a13 44 369 gnd - 29 37 c12 45 - 61. i/o - - - d13 46 375 62. i/o - - - d14 47 378 63. i/o - - 38 b13 48 381 64. i/o - - 39 a14 49 387 65. i/o - 30 40 a15 50 390 66. i/o - 31 41 c13 51 393 67. i/o 27 32 42 b14 52 399 68. i/o - 33 43 a16 53 402 69. i/o - 34 44 b15 54 405 70. i/o - 35 45 c14 55 411 71. i/o 28 36 46 a17 56 414 72. i/o 29 37 47 b16 57 417 73. m1 (i/o) 30 38 48 c15 58 426 gnd 31 39 49 d15 59 - 74. m0 (i/o) 32 40 50 a18 60 429 - - - 51* - - - - - - 52* - - - - - - 53* - - - - - - 54* - - - vcc 33 41 55 d16 61 - 75. m2 (i/o) 34 42 56 c16 62 432 76. gck2 (i/o) 35 43 57 b17 63 435 77. i/o (hdc) 36 44 58 e16 64 444 78. i/o - 45 59 c17 65 447 79. i/o - 46 60 d17 66 450 80. i/o - 47 61 b18 67 456 81. i/o (ldc) 37 48 62 e17 68 459 82. i/o - 49 63 f16 69 462 83. i/o - 50 64 c18 70 468 84. i/o - - 65 d18 71 471 85. i/o - - 66 f17 72 474 86. i/o - - - e15 73 480 87. i/o - - - f15 74 483 gnd - 51 67 g16 75 - 88. i/o - 52 68 e18 76 486 89. i/o - 53 69 f18 77 492 90. i/o 38 54 70 g17 78 495 91. i/o 39 55 71 g18 79 504 vcc ----80 - 92. i/o - - 72 h16 81 507 93. i/o - - 73 h17 82 510 - - - - - 83* - 94. i/o - - - g15 84 516 95. i/o - - - h15 85 519 96. i/o - 56 74 h18 86 522 97. i/o - 57 75 j18 87 528 98. i/o 40 58 76 j17 88 531 99. i/o ( err, init) 41 59 77 j16 89 534 vcc 42 60 78 j15 90 - gnd 43 61 79 k15 91 - 100. i/o 44 62 80 k16 92 540 pin description ? pc84 pq160 pq208 pg223 pq240 boundary scan order xc5210 pinouts * indicates unconnected package pins. ? leading number refers to bonded pad, shown in figure 21.
r 39 101. i/o 45 63 81 k17 93 543 102. i/o - 64 82 k18 94 546 103. i/o - 65 83 l18 95 552 104. i/o - - 84 l17 96 555 105. i/o - - 85 l16 97 558 - - - - - 98* - 106. i/o - - - l15 99 564 107. i/o - - - m15 100 567 vcc - - - - 101 - 108. i/o 46 66 86 m18 102 570 109. i/o 47 67 87 m17 103 576 110. i/o - 68 88 n18 104 579 111. i/o - 69 89 p18 105 588 gnd - 70 90 m16 106 - 112. i/o - - - n15 107 591 113. i/o - - - p15 108 600 114. i/o - - 91 n17 109 603 115. i/o - - 92 r18 110 606 116. i/o - 71 93 t18 111 612 117. i/o - 72 94 p17 112 615 118. i/o 48 73 95 n16 113 618 119. i/o 49 74 96 t17 114 624 120. i/o - 75 97 r17 115 627 121. i/o - 76 98 p16 116 630 122. i/o 50 77 99 u18 117 636 123. i/o 51 78 100 t16 118 639 gnd 52 79 101 r16 119 - - - - 102* - - - done 53 80 103 u17 120 - - - - 104* - - - - - - 105* - - - vcc 54 81 106 r15 121 - - - - 107* - - - prog 55 82 108 v18 122 - 124. i/o (d7) 56 83 109 t15 123 648 125. gck3 (i/o) 57 84 110 u16 124 651 126. i/o - 85 111 t14 125 660 127. i/o - 86 112 u15 126 663 128. i/o - - - r14 127 666 129. i/o - - - r13 128 672 130. i/o (d6) 58 87 113 v17 129 675 131. i/o - 88 114 v16 130 678 132. i/o - 89 115 t13 131 684 133. i/o - 90 116 u14 132 687 134. i/o - - 117 v15 133 690 135. i/o - - 118 v14 134 696 gnd - 91 119 t12 135 - 136. i/o - - - r12 136 699 137. i/o - - - r11 137 708 138. i/o - 92 120 u13 138 711 139. i/o - 93 121 v13 139 714 vcc - - - - 140 - 140. i/o (d5) 59 94 122 u12 141 720 141. i/o ( cs0) 60 95 123 v12 142 723 - - - - - 143* - 142. i/o - - 124 t11 144 726 143. i/o - - 125 u11 145 732 144. i/o - 96 126 v11 146 735 145. i/o - 97 127 v10 147 738 146. i/o (d4) 61 98 128 u10 148 744 147. i/o 62 99 129 t10 149 747 vcc 63 100 130 r10 150 - gnd 64 101 131 r9 151 - 148. i/o (d3) 65 102 132 t9 152 756 pin description ? pc84 pq160 pq208 pg223 pq240 boundary scan order 149. i/o ( rs) 66 103 133 u9 153 759 150. i/o - 104 134 v9 154 768 151. i/o - 105 135 v8 155 771 152. i/o - - 136 u8 156 780 153. i/o - - 137 t8 157 783 - - - - - 158* - 154. i/o (d2) 67 106 138 v7 159 786 155. i/o 68 107 139 u7 160 792 vcc ----161 - 156. i/o - 108 140 v6 162 795 157. i/o - 109 141 u6 163 798 158. i/o - - - r8 164 804 159. i/o - - - r7 165 807 gnd - 110 142 t7 166 - 160. i/o - - - r6 167 810 161. i/o - - - r5 168 816 162. i/o - - 143 v5 169 819 163. i/o - - 144 v4 170 822 164. i/o - 111 145 u5 171 828 165. i/o - 112 146 t6 172 831 166. i/o (d1) 69 113 147 v3 173 834 167. i/o ( rclk- busy/rdy) 70 114 148 v2 174 840 168. i/o - 115 149 u4 175 843 169. i/o - 116 150 t5 176 846 170. i/o (d0, din) 71 117 151 u3 177 855 171. i/o (dout) 72 118 152 t4 178 858 cclk 73 119 153 v1 179 - vcc 74 120 154 r4 180 - - - - 155* - - - - - - 156* - - - - - - 157* - - - - - - 158* - - - 172. i/o (tdo) 75 121 159 u2 181 - gnd 76 122 160 r3 182 - 173. i/o (a0, ws) 77 123 161 t3 183 9 174. gck4 (i/o, a1) 78 124 162 u1 184 15 175. i/o - 125 163 p3 185 18 176. i/o - 126 164 r2 186 21 177. i/o (cs1, a2) 79 127 165 t2 187 27 178. i/o (a3) 80 128 166 n3 188 30 179. i/o - - - p4 189 33 180. i/o - - - n4 190 39 181. i/o - 129 167 p2 191 42 182. i/o - 130 168 t1 192 45 183. i/o - - 169 r1 193 51 184. i/o - - 170 n2 194 54 - - - - - 195* - gnd - 131 171 m3 196 - 185. i/o - 132 172 p1 197 57 186. i/o - 133 173 n1 198 66 187. i/o - - - m4 199 69 188. i/o - - - l4 200 75 vcc ----201 - 189. i/o (a4) 81 134 174 m2 202 78 190. i/o (a5) 82 135 175 m1 203 81 - - - - - 204* - 191. i/o - - 176 l3 205 87 192. i/o - 136 177 l2 206 90 193. i/o - 137 178 l1 207 93 194. i/o - 138 179 k1 208 99 195. i/o (a6) 83 139 180 k2 209 102 196. i/o (a7) 84 140 181 k3 210 105 gnd 1 141 182 k4 211 - pin description ? pc84 pq160 pq208 pg223 pq240 boundary scan order xc5210 pinouts (continued) boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 666 = bscan.upd
xc5200 logic cell array family preliminary (v1.0) 40 physical dimensions 84-pin plastic plcc (pc84) 160-pin plastic pqfp (pq160) pin 1 id 0.045 x 45 1.190 0.005 1.154 0.004 1.154 0.004 1.190 0.005 33 11 75 53 top view 1 0.045 0.028 0.100 0.010 0.175 0.010 0.017 0.020 0.045 1.000 typ 1.120 0.010 side view 0.004 ?c x3426 dimensions in inches lead pitch 50 mil 12 32 74 54 31.20 sq 28.00 sq pin 1 id 160 121 140 80 41 81 120 0.28 0.05 3.38 0.20 dimensions in millimeters lead pitch 0.65 mm x3434 top view side view 0.10 ?c 5 - 7 stand-off 0.10-0.36
r 41 191-pin ceramic pga (pg191) 208-pin plastic pqfp (pq208) 1.860 0.019 sq 1.700 typ bottom view 0.050 x 45 pin #1 side chamfer 0.030 0.010 x 45 (3 places) stand-off pin (4 places) dielectric coat 0.070 dia typ (191 places) s/r 0.890 sq 0.090 0.010 0.050 0.010 0.130 0.010 0.008 (4 places) 0.050 x 0.025 0.018 0.002 au plated kovar 0.005 r typ 0.100 typ a b c d e f g h j k l m n p r t u v 123456789101112131415161718 top view top edge chamfer 0.010 x 45 typ gold plate pin #1 index top side dimensions in inches side view x3438 30.60 sq 28.00 sq pin 1 id 208 157 152 104 53 105 156 0.13 0.25 12 - 16 x3439 dimensions in millimeters lead pitch 0.50 0.08 ?c top view 3.67 3.17 side view stand-off 0.25 min 0.064 ref
xc5200 logic cell array family preliminary (v1.0) 42 223-pin ceramic pga (pg223) 240-pin plastic pqfp (pq240) 1.860 0.019 sq 1.700 typ bottom view 0.050 x 45 pin #1 side chamfer 0.030 0.010 x 45 (3 places) stand-off pin (4 places) dielectric coat 0.070 dia typ (223 places) s/r 0.899 max sq 0.090-0.110 0.050 0.010 0.130 0.010 0.008 (4 places) 0.050 x 0.025 0.018 0.002 au plated kovar 0.005 r typ 0.100 typ a b c d e f g h j k l m n p r t u v 123456789101112131415161718 x3441 top view top edge chamfer 0.010 x 45 typ gold plate pin #1 index top side dimensions in inches side view 60 #1pin 61 120 180 12?6 (2 halves) 181 240 121 pin 1 id 0.020 typ x3442 top view side view 3.50 3.30 dimensions in millimeters lead pitch 0.50 mm 34.60 32.00 stand-off 0.25 min 0.10 ?c 0.14-0.30
r 43 ordering information component availability number of available i/o pins pins 84 160 191 208 223 240 type plastic plcc plastic pqfp ceramic pga plastic pqfp ceramic pga plastic pqfp code pc84 pq160 pg191 pq208 pg223 pq240 xc5206 -7 ci ci ci ci -6 ci ci ci ci -5cccc xc5210 -7 ci ci ci ci ci -6 ci ci ci ci ci -5 ci ci ci ci ci c = commercial = 0 to +70 c i = industrial = -40 to +85 c device max i/o package type pc84 pq160 pg191 pq208 pg223 pq240 xc5206 148 65 133 148 148 xc5210 196 65 133 164 196 196 xc5210-6pq208c package type number of pins temperature range speed grade device type example:
the programmable logic company sm 2100 logic drive, san jose ca 95124-3400 tel: (408) 559-7778 fax: (408) 559-7114 r printed in u.s.a. p/n 0401300 e2 0401300

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